1. Field of the Invention
The present invention relates to programmable logic blocks, and more particularly to techniques for providing freeze logic for programmable logic blocks.
2. Description of Related Art
Programmable logic integrated circuits (ICs) include devices such as field programmable gate arrays (FPGAs), programmable logic devices (PLDs), and programmable logic arrays (PLAs). When a programmable logic IC is configured, nodes in the IC can enter undefined states, causing unwanted power consumption, contention between circuit elements, and possibly circuit failure.
Many FPGAs use a freeze methodology to prevent circuit contention during configuration mode. According to the freeze methodology, pre-defined voltage values are driven to interconnect lines in the IC and/or logic in the IC is disabled using freeze logic and other freeze signals during the configuration mode. The freeze logic implements the freeze methodology on all logic block outputs.
For example, on programmable logic array blocks in FPGAs made by Altera Corporation of San Jose, Calif., freeze logic is incorporated into the output logic of the logic elements (LEs) to properly disable the LE outputs, while the IC is frozen using a freeze logic signal. The freeze logic signal effectively disables the output multiplexers and forces the output driver to a high state, in accordance with the freeze methodology.
In the freeze methodology, each output multiplexer in each logic element requires its own control logic to disable the output of the multiplexer and to enable a weak pull down driver. The control logic in each multiplexer requires 3 inverters and 2 NAND gates, and a weak pull down to drive the output driver. Each logic element has 3 output multiplexers and 3 outputs. The freeze methodology is implemented on all LE outputs. Thus, the freeze methodology is expensive in terms of silicon real estate, because there are multiple outputs per LE, and the control logic is replicated for each output.
It would therefore be desirable to provide techniques for freezing a programmable logic IC during configuration mode that require less silicon area.